Coherent constant delay transceiver for a synchronous fiber optic network

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This paper proposes the implementation of a coherent transceiver with a constant delay and the ability to select any clock frequency grid used for clocking peripheral DACs and ADCs, tasks of device synchronization and data transmission. The choice of the required clock frequency grid directly affects the data transfer rate in the network, however, it allows one to flexibly configure the network for the tasks of transmitting clock signals and subnanosecond generation of sync signals on all devices in the network. A method for increasing the synchronization accuracy to tenths of nanoseconds by using digital phase detectors and a Phase Locked Loop (PLL) system on the slave device is proposed. The use of high-speed fiber-optic communication lines (FOCL) for synchronization tasks allows simultaneously exchanging control commands and signaling data. To simplify and reduce the cost of devices of a synchronous network of transceivers, it is proposed to use a clock signal restored from a data transmission line to filter phase noise and form a frequency grid in the PLL system for heterodyne signals and clock peripheral devices, including DAC and ADC. The results of multiple synchronization tests in the proposed synchronous network are presented.

Keywords: FPGA, FOCL, PLL, subnanosecond time synchronization, single time scale, two-way synchronization method, clock recovery, diversity in-phase clock network, generation of ADC and DAC clock signals
Citation in English: Deev A.A., Kalshchikov A.A. Coherent constant delay transceiver for a synchronous fiber optic network // Computer Research and Modeling, 2023, vol. 15, no. 1, pp. 141-155
Citation in English: Deev A.A., Kalshchikov A.A. Coherent constant delay transceiver for a synchronous fiber optic network // Computer Research and Modeling, 2023, vol. 15, no. 1, pp. 141-155
DOI: 10.20537/2076-7633-2023-15-1-141-155

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International Interdisciplinary Conference "Mathematics. Computing. Education"