Результаты поиска по 'FPGA':
Найдено статей: 2
  1. Belean B., Belean C., Floare C., Varodi C., Bot A., Adam G.
    Grid based high performance computing in satellite imagery. Case study — Perona–Malik filter
    Computer Research and Modeling, 2015, v. 7, no. 3, pp. 399-406

    The present paper discusses an approach to the efficient satellite image processing which involves two steps. The first step assumes the distribution of the steadily increasing volume of satellite collected data through a Grid infrastructure. The second step assumes the acceleration of the solution of the individual tasks related to image processing by implementing execution codes which make heavy use of spatial and temporal parallelism. An instance of such execution code is the image processing by means of the iterative Perona–Malik filter within FPGA application specific hardware architecture.

    Views (last year): 3.
  2. Deev A.A., Kalshchikov A.A.
    Coherent constant delay transceiver for a synchronous fiber optic network
    Computer Research and Modeling, 2023, v. 15, no. 1, pp. 141-155

    This paper proposes the implementation of a coherent transceiver with a constant delay and the ability to select any clock frequency grid used for clocking peripheral DACs and ADCs, tasks of device synchronization and data transmission. The choice of the required clock frequency grid directly affects the data transfer rate in the network, however, it allows one to flexibly configure the network for the tasks of transmitting clock signals and subnanosecond generation of sync signals on all devices in the network. A method for increasing the synchronization accuracy to tenths of nanoseconds by using digital phase detectors and a Phase Locked Loop (PLL) system on the slave device is proposed. The use of high-speed fiber-optic communication lines (FOCL) for synchronization tasks allows simultaneously exchanging control commands and signaling data. To simplify and reduce the cost of devices of a synchronous network of transceivers, it is proposed to use a clock signal restored from a data transmission line to filter phase noise and form a frequency grid in the PLL system for heterodyne signals and clock peripheral devices, including DAC and ADC. The results of multiple synchronization tests in the proposed synchronous network are presented.

Indexed in Scopus

Full-text version of the journal is also available on the web site of the scientific electronic library eLIBRARY.RU

The journal is included in the Russian Science Citation Index

The journal is included in the RSCI

International Interdisciplinary Conference "Mathematics. Computing. Education"